The present invention relates generally to semiconductor memory devices and more particularly to methods and memory apparatus with non-volatile ferroelectric capacitors for storing data in a semiconductor device.
In semiconductor memory devices, data is read from or written to the memory using address signals and various other control signals. In random access memories (xe2x80x9cRAMSxe2x80x9d), an individual binary data state (e.g., a bit) is stored in a volatile memory cell, wherein a number of such cells are grouped together into arrays of columns and rows accessible in random fashion along bitlines and wordlines, respectively, wherein each cell is associated with a unique wordline and bitline pair. Address decoder control circuits identify one or more cells to be accessed in a particular memory operation for reading or writing, wherein the memory cells are typically accessed in groups of bytes or words (e.g., generally a multiple of 8 cells arranged along a common wordline). Thus, by specifying an address, a RAM is able to access a single byte or word in an array of many cells, so as to read or write data from or into that addressed memory cell group.
Two major classes of random access memories include xe2x80x9cdynamicxe2x80x9d (e.g., DRAMs) and xe2x80x9cstaticxe2x80x9d (e.g., SRAMs) devices. For a DRAM device, data is stored in a capacitor, where an access transistor gated by a wordline selectively couples the capacitor to a bit line. DRAMs are relatively simple, and typically occupy less area than SRAMs. However, DRAMs require periodic refreshing of the stored data, because the charge stored in the cell capacitors tends to dissipate. Accordingly DRAMs need to be refreshed periodically in order to preserve the content of the memory. SRAM devices, on the other hand, do not need to be refreshed. SRAM cells typically include several transistors configured as a flip-flop having two stable states, representative of two binary data states. Since the SRAM cells include several transistors, however, SRAM cells occupy more area than do DRAM cells. However, SRAM cells operate relatively quickly and do not require refreshing and the associated logic circuitry for refresh operations.
A major disadvantage of SRAM and DRAM devices is volatility, wherein removing power from such devices causes the data stored therein to be lost. For instance, the charge stored in DRAM cell capacitors dissipates after power has been removed, and the voltage used to preserve the flip-flop data states in SRAM cells drops to zero, by which the flip-flop loses its data. Accordingly, SRAMs and DRAMs are commonly referred to as xe2x80x9cvolatilexe2x80x9d memory devices. Non-volatile memories are available, such as Flash and EEPROM. However, these types of non-volatile memory have operational limitations on the number of write cycles. For instance, Flash memory devices generally have life spans from 100 K to 10 MEG write operations.
Recently, non-volatile ferroelectric RAM devices have been developed, which are commonly referred to as FERAMs or FRAMs. FERAM cells employ ferroelectric cell capacitors including a pair of capacitor plates with a ferroelectric material between them. Ferroelectric materials have two different stable polarization states that may be used to store binary information, where the ferroelectric behavior follows a hysteresis curve of polarization versus applied voltage. FERAMs are non-volatile memory devices, because the polarization state of a ferroelectric cell capacitor remains when power is removed from the device. Ferroelectric memories provide certain performance advantages over other forms of non-volatile data storage devices, such as Flash and EEPROM type memories. For example, ferroelectric memories offer short programming (e.g., write access) times and low power consumption. However, access times in SRAM and DRAM type memories are significantly shorter than in FERAM devices.
Hybrid memory devices have been developed, which include volatile and non-volatile portions. For example, memories have been constructed combining SRAM cells with ferroelectric devices, wherein the memory may be operated as an SRAM, with the capability to backup or save the volatile SRAM data to ferroelectric capacitors associated with the SRAM cells. The non-volatile data may thereafter be retrieved from the ferroelectric capacitors and transferred to the SRAM cells. In the interim, the SRAM cells may be operated as normal SRAM, even while non-volatile data resides in the ferroelectric capacitors. However, problems exist in current hybrid memory devices. For example, in transferring data between the SRAM cell and the associated ferroelectric capacitors, the relative capacitance of the internal SRAM cell nodes and the ferroelectric devices reduces the voltage margins for sensing data and for polarizing the ferroelectric capacitors. Accordingly, there is a need for improved hybrid memory cell apparatus combining SRAM or other volatile memory cells with non-volatile ferroelectric capacitors for storing data in a semiconductor device.
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
One aspect of the invention relates to methods and memory apparatus for storing data in a semiconductor device, where the apparatus comprises a volatile portion and a non-volatile portion. The volatile portion is adapted to store a binary volatile data state and comprises first and second internal nodes. The non-volatile portion is coupled with the first and second internal nodes of the volatile portion and is adapted to store a binary non-volatile data state. The non-volatile portion comprises first and second ferroelectric capacitors coupled with the first internal node of the volatile portion, as well as third and fourth ferroelectric capacitors coupled with the second internal node of the volatile portion.
The volatile portion may be any form or type of volatile memory cell having two internal nodes, where the electrical state of the nodes is indicative of a binary data state stored therein. In one example, the volatile portion comprises an SRAM cell, including a first inverter comprising a first input coupled with the second internal node and a first output coupled with the first internal node, as well as a second inverter comprising a second input coupled with the first internal node and a second output coupled with the second internal node. Switching circuits may be provided to selectively couple first and/or second supply nodes in the SRAM cell with a supply voltage or a ground.
A control circuit may also be included to provide timing and control signals to the volatile and non-volatile portions during memory operations in the memory apparatus. In one implementation of the invention, the first and third ferroelectric capacitors are coupled with a first plateline signal, and the second and fourth ferroelectric capacitors are coupled with a second plateline signal. This facilitates provision of different plateline voltage signals thereto during FERAM read and write operations. In addition, the non-volatile portion may further comprise a coupling circuit for selectively coupling the first and second ferroelectric capacitors with the first internal node and for coupling the third and fourth ferroelectric capacitors with the second internal node according to a ferroelectric enable signal from the control circuit.
Another aspect of the invention provides a memory apparatus for storing data in a semiconductor device, which comprises an SRAM memory cell including first and second internal nodes and first and second supply nodes, and which is adapted to store a binary volatile data state. The apparatus further comprises a non-volatile memory cell coupled with the first and second internal nodes of the SRAM cell and adapted to store a binary non-volatile data state. The non-volatile portion comprises first and second ferroelectric capacitors coupled with the first internal node of the volatile portion, and third and fourth ferroelectric capacitors coupled with the second internal node of the volatile portion. The apparatus also includes a first switching circuit adapted to selectively couple the first supply node with a supply voltage or a ground and a second switching circuit adapted to selectively couple the second supply node with the supply voltage or ground.
Yet another aspect of the invention provides a memory apparatus, comprising an SRAM memory cell including first and second internal nodes and first and second supply nodes, and first and second ferroelectric capacitors coupled with one of the first and second internal nodes of the SRAM memory cell, the ferroelectric capacitors being adapted to store a binary non-volatile data state. Still another aspect of the invention provides methods for storing data in a semiconductor device, in which first and second plateline signals are provided to different ferroelectric capacitors in the non-volatile memory portion, wherein the second plateline signal is different from the first plateline signal in at least a portion of one of a non-volatile read operation or a non-volatile write operation.
To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.